# The CAN Protocol Tour

## CAN Bit Timing

### The Layout of a Bit

Each bit on the CAN bus is, for timing purposes, divided into at least 4 quanta. The quanta are logically divided into four groups or segments -

- the Synchronization Segment
- the Propagation Segment
- the Phase Segment 1
- the Phase Segment 2

Here is a picture of a CAN data bit:

###### Helpful Tools

#### Bit Timing Calculator

Use the calculator to calculate all possible sets of CAN bus parameters for a given input frequency and a given bus speed.

The Synchronization Segment, which always is one quantum long, is used for synchronization of the clocks. A bit edge is expected to take place here when the data changes on the bus.

The Propagation Segment is needed to compensate for the delay in the bus lines.

The Phase Segments may be shortened (Phase Segment 1) or lengthened (Phase Segment 2) if necessary to keep the clocks in sync.

The bus levels are sampled at the border between Phase Segment 1 and Phase Segment 2.

Most CAN controllers also provide an option to sample three times during a bit. In this case, the sampling occurs on the borders of the two quanta that precedes the sampling point, and the result is subject to majority decoding (at least this is the case for the 82527.)

### Clock Synchronization

In order to adjust the on-chip bus clock, the CAN controller may shorten or prolong the length of a bit by an integral number of quanta. The maximum value of these bit time adjustments are termed the Synchronization Jump Width, SJW.

**Hard synchronization **occurs on the recessive-to-dominant transition of the start bit. The bit time is restarted from that edge.

**Resynchronization **occurs when a bit edge doesn’t occur within the Synchronization Segment in a message. One of the Phase Segments are shortened or lengthened with an amount that depends on the phase error in the signal; the maximum amount that may be used is determined by the Synchronization Jump Width parameter.

### Bit Timing Register Calculation

Most CAN controllers allows the programmer to set the bit timing using the following parameters:

- A clock prescaler value
- The number of quanta before the sampling point
- The number of quanta after the sampling point
- The number of quanta in the
*Synchronization Jump Width*, SJW

Usually two registers are provided for this purpose: btr0 and btr1. Things tend to vary slightly between different controllers, however, so read your data sheets carefully.

On the 82c200 and SJA1000, both from NXP (nee Philips), the register layout is like this:

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |

btr0 | SJW1 | SJW0 | BRP5 | BRP4 | BRP3 | BRP2 | BRP1 | BRP0 |

btr1 | SAM | TSEG22 | TSEG21 | TSEG20 | TSEG13 | TSEG12 | TSEG11 | TSEG10 |

- BRP0..BRP5 sets the clock prescaler value
- SJW0..SJW1 sets the length of the SJW
- TSEG10..TSEG13 sets the number of quanta before the sampling point (the start bit is not included)
- TSEG20..TSEG22 sets the number of quanta after the sampling point.
- SAM is set to 1 if three samples is to be obtained and to 0 if one sample is enough.

*Note: the actual value of these parameters is one more than the value written into the register.*

Example: if the oscillator signal fed to the SJA1000 is 16 MHz, and we want a bit rate of 250 kbit/s, with a sampling point close to 62% of the whole bit, and a SJW of 2 quanta, we can set -

BRP = 4, which gives a quantum length of 2 * 4 / 16000000 s = 500 ns, and

TSEG1 = 5, which gives 5 quanta before the sampling point, and

TSEG2 = 3, which gives 3 quanta after the sampling point.

Each bit will then comprise 5 + 3 = 8 quanta, which results in the desired bit rate of 1 / (8 * 500 ns) = 250 kbit/s. The register values should then be

btr0 = | (SJW – 1) * 64 + (BRP -1) = (2-1)*64 + (4-1) = 67 = 0×43 |

btr1 = | SAM * 128 + (TSEG2 – 1)* 16 + (TSEG1 – 1) = 0*128 + (3-1)*16 + (4-1) = (“4″ because the start bit isn’t included)35 = 0×23 |

The sampling point is at 5/8 = 62.5% of a bit.